In modern computing systems, multiple processors can be present and each such processor may execute different threads of code of a common application. To maintain consistency, data synchronization mechanisms may be used. One such technique includes the use of transactional memory (TM). Often transactional execution includes executing a grouping of a plurality of micro-operations, operations, or instructions. Each of multiple threads may execute and access common data within a memory structure. If both threads access/alter the same entry within the structure, conflict resolution may be performed to ensure data validity. One type of transactional execution includes Software Transactional Memory (STM), where tracking of memory accesses, conflict resolution, abort tasks, and other transactional tasks are performed in software, generally without the support of hardware.
Another type of transactional execution includes a Hardware Transactional Memory (HTM) system, where hardware is included to support access tracking, conflict resolution, and other transactional tasks. Previously, actual memory data arrays were extended with additional bits to hold information, such as hardware attributes to track reads, writes, and buffering, and as a result, the data travels with the data from the processor to memory. Often this information is referred to as persistent, i.e. it is not lost upon a cache eviction, since the information travels with data throughout the memory hierarchy. Yet, this persistency imposes more overhead throughout the memory hierarchy system.
Yet another type of TM model is referred to as an unbounded transactional memory (UTM), which enables arbitrarily large transactions in time and memory footprint to occur through a combination of hardware acceleration using hardware and software. Running and implementing UTM transactions typically require specially compiled code for implementing concurrency control mechanisms with UTM hardware acceleration interfaces. As a result, UTM transactions can be complex and may not correctly interact with existing hardware and STM transactional systems.